1. Field of the Invention
The invention relates to a computing system, more particularly to a method for enabling a digital signal processor in a computing system to access parameter tables through a central processing unit.
2. Description of the Related Art
A central processing unit (CPU) is responsible for peripheral components control, logic operations, arithmetic operations, instructions decoding and execution, etc., and is the control center of a computer system. Since the main function of the central processing unit is peripheral components control, the central processing unit is suitable for performing only simple arithmetic operations like addition and subtraction, and is not suitable for performing complex mathematical computations or logic operations. When the central processing unit is instructed to perform the complex mathematical computations or logic operations, poor operating efficiency (i.e., low computational speed or even inoperability) will occur. A digital signal processor (DSP) is specially designed for performing complex arithmetic computations involving addition, subtraction, multiplication and division, and complex logic operations in a low power but highly efficient manner. Therefore, a central processing unit usually operates in combination with a digital signal processor for improving digital computation efficiency in a system, such as a digital versatile disc (DVD) player, or a mobile phone, etc.
FIG. 1 illustrates a conventional system 1 that incorporates a digital signal processor (DSP) 11. The DSP 11 is electrically connected to an external input/output (I/O) interface 13 and a memory unit 12. The memory unit 12 includes a read-only memory (ROM) 121 and a random access memory (RAM) 122, and stores program code and data for the operations of the DSP 11. In general, the digital computations performed by the DSP 11 involve algorithms that require the use of parameter tables. For example, in voice recognition applications, parameter tables are needed for judgment after analytical computation of sound. Moreover, in the formula Y=aX^2+bX+c, where X is an input signal, Y is an output signal, and a, b and c are parameters, the number of possible results could be quite enormous in view of the possible combinations of the parameters (a, b, c). For example, assuming that a, b, c are 4-bit data, the possible combinations can amount to 16*16*16≈4000. Parameter tables formed from the possible parameter combinations can be stored in the ROM 121 beforehand such that, when needed by the DSP 11, the relevant data can be retrieved from the memory unit 12 through appropriate addressing. This method of memory access is called direct addressing and can be completed in one computing cycle. The external I/O interface 13 is electrically connected to an external circuit. Thus, the DSP 11 can be used for digital computations in order to improve the system computing efficiency.
At present, the data width of the DSP 11 is widely designed as 16 bits. The addressable space of the DSP 11 is thus limited to 64 KB (216=64 KB). If the size of the parameter tables is more than 64 KB, the parameter tables cannot be stored in the memory unit 12. In practice, limitations on the size of the parameter tables may be even more restricted, because the addressable space must include the ROM 121, the RAM 122 and a memory map for the external I/O interface 13. Therefore, the size of the addressable space allocated for the parameter tables is actually less than 64 KB. Moreover, the system 1 of FIG. 1 is usually designed as a single packaged chip. In view of cost and size considerations, the capacity of the memory unit 12 is usually only around 2 KB. Since the memory unit 12 has space reserved for storing program code and other data, it is evidently impractical for parameter tables having sizes greater than 1 KB to be stored in the memory unit 12 for data access by the DSP 11 using the conventional direct addressing method.
In many applications, such as digital signal processing in voice recognition, image processing, mobile phone communications and video signal interfacing, etc., the size of parameter tables is generally larger than 64 KB. Thus, the parameter tables cannot be stored in the memory unit 12. Therefore, the system 1 must be configured to cooperate with an external memory having slower access speed (such as flash memory or dynamic random access memory). The external memory configuration is shown in FIG. 2. As illustrated, the external I/O interface 13′ of a system 1′ that is identical in structure to the system 1 of FIG. 1 is coupled to an external memory 21 which has the parameter tables stored therein. The external I/O interface 13′ relies upon indirect addressing to access data from the external memory 21.
The following are some of the drawbacks associated with the conventional configuration of FIG. 2:
1. Additional external circuits are needed. Because the external memory 21 is accessed by indirect addressing, there is a need to provide an address register 22 for temporary storage of the address of requested data, a data register 23 for temporary storage of data retrieved from the external memory 21, and an access control circuit 24 (for example, a direct memory access (DMA) controller) so that data corresponding to the address in the address register 22 may be retrieved from the external memory 21 and stored in the data register 23 for subsequent use by the DSP 11′ in the system 1′, thereby resulting in increased components costs.
2. Computing time is increased. When the DSP 11′ accesses the parameter tables through the external circuits 22, 23 and 24, an address is first written into the address register 22, and the access control circuit 24 then retrieves the requested data from the external memory 21 in accordance with the address in the address register 22 and stores the requested data in the data register 23 for subsequent access by the DSP 11′ through the external I/O interface 13′. Therefore, instead of directly accessing data from an internal memory unit 12 as done by the DSP 11 in the aforesaid system 1 of FIG. 1, extra steps are required for reading data through the external circuits 22, 23 and 24 such that data reading cannot be completed in one computing cycle. Moreover, when the DSP 11′ issues a request for data, the DSP 11′ cannot proceed with other operations until the requested data is provided thereto. Therefore, the computing time is increased, and the computing efficiency and speed of the DSP 11′ are decreased.
The data width of a commercially available central processor unit is 32 bits, thus resulting in an addressable space of as high as 4 gigabytes (232≈4*106). The capacity of a computer memory (for example, flash memories, dynamic random access memories, etc.) used with a central processing unit can also be enormous. Together, the central processing unit and the computer memory will have adequate addressable space and memory capacity for parameter table utilization. Since a central processing unit has an inherent memory access function and is used in combination with a digital signal processor, if a method for enabling the digital signal processor in a computing system to access parameter tables through the central processing unit is provided, the aforesaid drawbacks can be overcome.